The present invention generally relates to microprogram branching methods and microsequencers employing such microprogram branching methods, and more particularly to a microprogram branching method and a microsequencer employing the microprogram branching method for realizing a high-speed branch process with a reduced number of program steps. The present invention is suited for application to a direct memory access controller (DMAC) which employs an internal control system using microprograms.
Generally, when constructing a microcomputer system, various peripheral large scale integrated circuits (LSIs) are required in addition to a central processing unit (CPU), and the DMAC is one of such peripheral LSIs. With the increase of the number of bits of the CPU to 16 or 32 bits, for example, there is now a demand for high performance DMACs which have a large number of functions. For this reason, there are proposed DMACs which employ the internal control system using microprograms, and the design facility and flexibility of the DMACs are improved together with the improved functions thereof.
FIG. 1 shows an essential part of an example of a conventional DMAC, that is, a microsequencer of the conventional DMAC. In FIG. 1, the microsequencer includes a micro read only memory (ROM) 10 which stores microprograms, an increment circuit 11 which generates a continue address C.sub.A by incrementing (adding +1 to) an address which is presently executed, an address register 12 which latches the continue address C.sub.A, a start address generating circuit 13 which generates a predetermined start address S.sub.A in response to a predetermined start signal START, a discriminating circuit 14 which discriminates whether or not a branch is to be made depending on various predetermined branch conditions, and a selection circuit 15 which operates responsive to a discrimination result obtained in the discriminating circuit 14. The selection circuit 15 normally selects the continue address C.sub.A, selects the start address S.sub.A when the start signal START is received, and selects the data (a branch address J.sub.A ') obtained from the micro ROM 10 when the branch is to be made.
Normally, according to this microsequencer, the data within the micro ROM 10 is successively obtained depending on the continue address C.sub.A and a required operation is carried out in an operation execution part (not shown) so as to carry out various functions of the DMAC. In addition, the branch address J.sub.A ' is selected depending on an operation information obtained from the operation execution part or status information (so-called branch conditions) obtained from various registers (not shown), and a branch process is carried out by executing a predetermined sub program indicated by the branch address J.sub.A '.
The branch process is carried out as follows, for example. That is, when the discriminating circuit 14 determines the branch conditions after examining the branch conditions and the data read out from the micro ROM 10 in an arbitrary step, the selection circuit 15 selects the branch address J.sub.A ' at this point in time and a new branch address J.sub.A ' is read out from the address of the micro ROM 10 indicated by the branch address J.sub.A '. Then, the micro ROM 10 is addressed by the new branch address J.sub.A ' and the process advances to the data processing of the branch address.
However, in the conventional DMAC, the branch address information is stored in the same microprogram. For this reason, when a branch is to be made, for example, an addressing operation must be carried out in duplicate by once obtaining the branch address J.sub.A ' from the microprogram and then obtain the new branch address J.sub.A ' for designating the sub program based on the previously obtained branch address J.sub.A '. In other words, there is a problem in that the efficiency of the branch process is poor.
FIG. 2 shows an example of the branch addresses stored in the micro ROM 10. For example, a branch instruction "JMP A(20)" at an address "10" instructs a branch to an address "20" when certain branch conditions are satisfied. When the branch is made, a branch instruction "JMP B(30)" instructs a branch to an address "30" when certain branch conditions are satisfied. In this typical example, it takes three clock cycles to process the two branch instructions as may be seen from FIGS. 3(A) through 3(C). FIG. 3(A) shows a clock signal CLK, where P and D respectively denote precharge and discharge times of the micro ROM 10. FIGS. 3(B) and 3(C) respectively show the address ADR and the data DATA.
Especially in the case of recent DMACs which are provided with a plurality of kinds of transfer functions, there is a need to frequently carry out a branch process to switch the functions. Hence, the above described problem is particularly notable in this case.